// MISSION BRIEF
LEVEL 01
AND Gate
Connect two inputs to an AND gate. The output should be HIGH only when both A and B are HIGH.
TRUTH TABLE
OBJECTIVE
GATE LIBRARY — drag to canvas
// SIGNAL MONITOR
Press SIMULATE to
evaluate circuit
evaluate circuit
IDLE
// VERILOG OUTPUT
// Run simulation to
// generate Verilog
// generate Verilog
// MISSION SELECT